1. Field of the Invention
The present invention generally relates to an improved method and apparatus for computer-aided electrical circuit design through circuit simulation and, more particularly, to a method and apparatus that combines circuit partitioning and modified nodal formulation to formulate matrices having particular properties which involve solution methods specialized to those properties.
2. Description of the Prior Art
Computer-aided electrical circuit simulators are a vital engineering tool. They apply the vast computational power of the computer to the analysis of very complicated circuits which would be tedious if not impossible to solve by hand.
Many techniques have been developed to make computer-aided simulation of large circuits more efficient. Most early computer-aided circuit simulators rely on classic nodal formulation to model the electrical circuits. Classic nodal formulation is based on Kirchhoff's Current Law (KCL) wherein the voltage at each node within the circuit is solved for by equating the sum of all branch currents entering that node to zero. The resultant nodal equations are put into matrix form and solved.
Chung-Wen Ho et al., The Modified Nodal Approach to Network Analysis, IEEE Transactions on Circuits, Vol. Cass-22, No. 6, Jun. 1975, which is herein incorporated by reference, notes that circuit simulators, which use classic nodal formulation methods, treat voltage sources inefficiently and are incapable of including either linear or non-linear current-dependent elements. Ho et al. discloses a modified nodal approach which attempts to improve efficiency by assigning to node branches containing such elements additional branch current variables and formulating corresponding branch constitutive relations as additional system equations. For a circuit not containing voltage sources or current-dependent elements, no new variables are introduced and the modified nodal formulation method is reduced to classic nodal formulation.
Other computer-aided circuit simulators, such as MOSART, which is described by Carlin et al., On Partitioning for Waveform relaxation Time-Domain Analysis of VLSI Circuits, IEEE, 1984, and is herein incorporated by reference, have attempted to improve electrical circuit efficiency by using partitioning techniques which partition large electrical circuits into smaller, sub-circuits which are easier to handle. Each sub-circuit is then analyzed over the entire time interval of the simulation.
Electrical or thermal modeling of electrical circuit networks often involves large passive RC networks which are often represented by thousands of equations which must be solved simultaneously. Popular circuit simulators, such as SPICE or ASTAP, use either modified nodal or hybrid tableau formulation to form a system matrix or matrices representative of the electrical circuit. Attempts to analyze such networks with such circuit simulators require extensive computer run time or excessive data storage requirements, or both. These drawbacks result because these simulators assume that the system matrix is arbitrary and use a general matrix solution method, such as Gaussian elimination, or the like, to solve the matrix. As a general rule, the system matrix or matrices formed by these simulators is arbitrary, and more particularly, they are not positive-definite symmetric.
ASTAP is based on the Hybrid Tableau circuit analysis and therefore can never produce a symmetric system matrix. SPICE uses modified nodal formulation; however, if a non-linear voltage or current source is present in the circuit, then the resultant system matrix is not symmetric.
All of the above mentioned computer-aided circuit simulators produce a system matrix or matrices which are arbitrary, and subsequently solved by some general matrix solving technique.